This invention relates to a semiconductor integrated circuit device, and a production and operation method thereof. More particularly, this invention relates to a technology that will accomplish high integration density, high reliability and low operating voltage of an electrically programmable/erasable non-volatile semiconductor memory device.
Among electrically programmable/erasable nonvolatile semiconductor memory devices, a so-called xe2x80x9cflash memoryxe2x80x9d is known as a memory device capable of collectively erasing data. The flash memory has excellent portability and impact resistance, and can electrically and collectively erase the data. Therefore, the demand for the flash memory has been increasing rapidly in recent years as a file (memory device) for compact personal digital assistants such as portable personal computers, digital still cameras, and so forth. To expand the market, reduction of a bit cost by the reduction of a memory cell area is of utmost importance, and various memory cell systems for accomplishing this object have been proposed as described in, for example, xe2x80x9cOhyo Butsuri (or Applied Physics)xe2x80x9d, Vol. 65, No. 11, p 1114-1124 published by the Japan Society of Applied Physics, Nov. 10, 1996.
On the other hand, JP-B-2,694,618 (Reference 1 corresponding to U.S. Ser. No. 204,175 filed on Jun. 8, 1988) describes a virtual ground type memory cell that uses a three-layered polysilicon gate. In other words, this memory cell comprises a semiconductor region formed in a well of a semiconductor substrate and three gates. The three gates are a floating gate formed on the well, a control gate formed on the floating gate and an erase gate formed between the control gate and the floating gate adjacent to each other. Each of the three gates comprises polysilicon and is isolated by an insulator film. The floating gate and the well, too, are isolated from each other by an insulator film. The control gate is connected in a row direction and constitutes a word line. A source/drain diffusion layer is formed in a column direction and shares the diffusion layer with an adjacent memory cell in a virtual ground type. The pitch in the column direction is thus reduced. The erase gate is in parallel with a channel and is disposed between the word lines (control gates) also in parallel with the word lines.
To execute program the memory cell in this Reference 1, mutually independent positive voltages are applied to the word line and to the drain, respectively, while the well, the source and the erase gate are kept at 0 V. In consequence, hot electrons develop in the channel portion in the proximity of the drain, the electrons are injected into the floating gate and the threshold voltage of the memory cell rises. To erase the memory content, a positive voltage is applied to the erase gate while the word line, the source/drain and the well are kept at 0 V. Consequently, the electrons are ejected from the floating gate to the erase gate and the threshold voltage drops.
JP-A-9-321157 (Reference 2, laid-open on Dec. 12, 1997), for example, discloses a split gate type memory cell. A large overlap area is secured between a diffusion layer and a floating gate so that the potential of the diffusion layer increases the potential of the floating gate. A low voltage is applied to a word line so as to improve the generation of hot electrons and the injection effect when data is written.
Furthermore, xe2x80x9cInternational Electron Devices Meeting Technical Digestxe2x80x9d, 1989, pp. 603-606 (Reference 3) discusses a method that controls a floating gate potential by a word line and controls a split channel by a third gate that is different from both floating gate and control gate.
However, the inventors of the present invention have found that several problems develop when a higher integration density is sought in the memory cells described above. Incidentally, the problems that follow are noticed by the present inventors and are not particularly known in the art.
First, in order to miniaturize a memory cell, scale-down in a direction vertical to an extending direction of a data line (that is, the direction of the arrangement of the data line) as well as scale-down in a direction vertical to an extending direction of a word line (that is, the direction of the arrangement of the word line) must be achieved. Reduction of the word line width and the word line gap is effective for achieving the reduction in the word line arrangement direction. However, when the word line width is decreased, the resistance value of the word line increases with the result that the rise of the word line voltage is retarded when the data is written or read out. This invites in turn the problem of the drop of the operation speed. To solve this problem, a stacked film of a polysilicon film and its metal silicide film (that is, a so-called xe2x80x9cpolycide filmxe2x80x9d) may be used in place of the polysilicon single film as a word line material. The polycide film provides a film having a lower resistance value than the polysilicon film having the same film thickness and can restrict the rise of the word line resistance. When miniaturization further proceeds in future and the word line with is required to be smaller than as it now is, a stacked film of the polysilicon film and a metal film (that is, a so-called xe2x80x9cpolymetal filmxe2x80x9d) may be used. The polymetal film can further lower the resistance value than the polycide film having the same film thickness and can cope with the further reduction of the word line width.
However, the following problems develop when the polycide film or the polymetal film is used as the word line material. In the memory cell described in the reference cited above, the erase gate and the word line are so arranged as to extend in the direction vertical to the data line direction. In order to reduce the gap between the word lines to twice the minimum feature size, it is necessary to pattern continuously the word line and the floating gate, then to form the insulator film between the floating gates so formed, and to form thereafter the erase gate. However, metals contained in the polycide or in the polymetal dissolve during a cleaning step as a pre-step for forming the insulator film between the floating gate and the erase gate. The dissolving metals again adhere to the sidewalls of the floating gate and are entrapped into the insulation film during the subsequent formation step of the insulator film. As a result, the defect density of the insulatot film increases and reliability is spoiled.
Second, the memory cell described in the above-mentioned reference employs a memory cell structure called a xe2x80x9csplit channel typexe2x80x9d in which the floating gate does not exist at a part of the channel portion. Control of the split channel in this memory cell is achieved as the potential of the control gate (word line) existing on that split channel is controlled. Therefore, the word line has also the function of the split gate.
Incidentally, to write the data into the memory cell, it is necessary to increase the occurrence quantity of hot electrons and injection efficiency. To attain this object, it is effective to increase the potential of the floating gate so as to increase the electric field in the vertical direction of the channel portion, and to lower the potential of the split gate to increase the electric field in the channel horizontal direction.
In the memory cell described in the Reference 1, however, the voltage of the split gate is controlled through the word line voltage. Therefore, the voltages of the floating gate and the split gate cannot be controlled independently. In other words, there is no way but to control the voltages of both floating gate and split gate through the word line voltage. In consequence, the generation of the hot electrons and injection efficiency cannot be improved simultaneously. When the data is programmed, therefore, an extremely large current with respect to the injection current flows, and the data cannot be programmed simultaneously into a plurality of memory cells. Furthermore, a high programming rate cannot be acquired.
Means described in the Reference 2 may be used as the method that simultaneously increases the generation of the hot electrons and injection efficiency in the split channel type memory cell. However, this method involves the problem in that that overlap between the diffusion layer and the floating gate becomes more difficult to secure with scale-down.
It may be possible to control the floating gate voltage through the word line and to control the split channel by using the third gate different from the floating gate and the control gate, on the basis of the technology described in the Reference 3. However, this technology does not take scale-down into consideration.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device suitable for miniaturization and having a high operation speed but a low defect density, and a production method of such a device.
The above and other objects and novel features of the present invention will become more apparent from the following description of the specification when taken in connection with the accompanying drawings.
The semiconductor integrated circuit device according to the present invention employs the construction wherein third gates having different functions from those of floating gate and control gate are buried in the gaps between word lines (control gate, second gate) and floating gates (first gate) existing in a direction vertical or parallel to the word lines.
Outlines of the present invention will be recited below.
1. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type so formed inside said well as to extend in a first direction, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and insulated from said first gate through a third insulator film, wherein the third gate is so formed as to extend in the first direction and is buried in a space between said first gates.
2. In a semiconductor integrated circuit device according to item 1, the first gates are formed symmetrically with respect to the third gate, and the third gates are formed symmetrically with respect to the first gate.
3. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region so formed inside the well as to extend in a first direction, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate, wherein end faces of the third gate are end faces opposing the first gates adjacent to each other between the first gates, and are so formed as to oppose end faces of the first gate existing in parallel with the first direction through the third insulator film.
4. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate over a second insulator film and a third gate formed and isolated from the first gate through a third insulator film, wherein an upper surface of the third gate exists at a position lower than the upper surface of the first gate.
5. A semiconductor integrated circuit device according to any one of items 1 to 4 has any one of the following constructions: a first construction wherein the first gate is a floating gate, the second gate is a control gate and the third gate is an erase gate; a second construction wherein the first gate is a floating gate, the second gate is a control gate and the third gate is a gate for controlling a split channel; and a third construction wherein the first gate is a floating gate, the second gate is a control gate and the third gate is a gate having the functions of both erase gate and gate for controlling a split channel.
6. In a semiconductor integrated circuit device according to item 5, a part of the third gate exists over the semiconductor region of the second conductivity type.
7. In a semiconductor integrated circuit device according to any one of items 1 to 4, the first gate is a floating gate, the second gate is a control gate and the third gate is an erase gate; and an entire surface of the third gate exists over the semiconductor region of the second conductivity type.
8. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and a third gate formed and isolated from the first gate through a third insulator film, wherein the third gate has functions of both erase gate and gate for controlling a split channel.
9. In a semiconductor integrated circuit device according to any one of items 1 to 8, the third insulator film is a silicon oxide film doped with nitrogen.
10. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and a third gate formed and isolated from the first gate through a third insulator film, wherein a film thickness of the first insulator film is greater than that of the second or third insulator film.
11. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and third gate formed and isolated from the first gate through a third insulator film, wherein the second gate comprises a stacked film of a polysilicon film and a metal silicide film, and the third gate exists as it is buried into a space between the first gates.
12. In a semiconductor integrated circuit device according to item 11, the metal silicide film is a tungsten film.
13. A semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and a third gate formed and isolated from the first gate through a third insulator film, wherein the second gate comprises a stacked film containing a metal film.
14. In a semiconductor integrated circuit device according to item 13, the second gate comprises a laminate film of a polysilicon film, a barrier metal film and a metal film.
15. In a semiconductor integrated circuit device according to item 13 or 14, the third gate exists as it is buried into the space between the first gates.
16. In a semiconductor integrated circuit device according to item 13, 14 or 15, the barrier metal film belongs to a group of a tungsten film, a titanium film, a tantalum film, a metal film made of a transition metal itself or its nitride film or its silicide film, an aluminum nitride film, a cobalt silicide film, a molybdenum silicide film, a titanium tungsten film or their alloy films.
17. A semiconductor integrated circuit device according to any one of items 11 to 16 has any of the following constructions: a first construction wherein the space between said first gates is defined by end faces of the first gates parallel to the extending direction of the second gates among the end faces of the first gates; and a second construction wherein the space between the first gates is defined by end faces of the first gates vertical to the extending direction of the second gates among the end faces of the first gates.
18. A semiconductor integrated circuit device includes a well of a first conductivity type formed in a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, local source lines and local data lines formed by connecting the semiconductor region, select transistors for selecting the local source line and the local data lines, a first gate formed over the semiconductor integrated substrate through a first insulator film, a second gate formed and isolated from the first gate through a second insulator film, word lines formed by connecting the second gates, and a third gate formed and isolated from the first gate through a third insulator film and having different functions from the first and second gates and, wherein a bundling portion of the third gates exists between the word line existing at the nearest position to the select transistor inside a memory cell block comprising the select transistors and the gate of the select transistor.
19. In a semiconductor integrated circuit device according to item 18, a dummy gate exists between the bundling portion of the third gates and the word line existing at the nearest position to the select transistor inside the memory cell block.
20. A semiconductor integrated circuit device according to item 18 or 19 has any one of the following constructions: a first construction wherein all of the third gates existing inside the memory cell are bundled at either one, or both of the ends of the memory cell block end; and a second construction wherein every other of the third gates existing inside the memory cell block are bundled at the memory cell block end.
21. A semiconductor integrated circuit device according to item 20 has any of the following constructions: a first construction wherein contact holes are disposed at the bundling portion of the third gates; and a second construction wherein the third gate and the dummy gate are connected through a contact hole and a metal wire.
22. In an operation method of a semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the third gate, the well and a source as one of the regions of the semiconductor region is applied to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to a voltage of the control gate to the third gate.
23. In an operation method of a semiconductor device includes a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a negative voltage relative to voltages of the third gate, the well and a source as one of the regions of the semiconductor region to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the third gate.
24. In an operation method of a semiconductor integrated circuit device includes a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a positive voltage relative to voltages of the third gate, the well and a source as one of the regions of the semiconductor region to a control gate as the second gate; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the third gate.
25. In an operation method of a semiconductor integrated circuit device includes a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the third gate and a source as one of the regions of the semiconductor region to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a negative voltage relative to the voltage of the well to the control gate while keeping the voltage of the third gate at 0 V.
26. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the third gate, the well and a source as one of the regions of the semiconductor region to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the well.
27. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a negative voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a negative voltage relative to the voltage of the well to the control gate while the voltage of the third gate is kept at 0 V.
28. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a negative voltage relative to voltages of the third gate, the well and a source as one of the regions of the semiconductor layer to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the well.
29. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film; the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the third gate.
30. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate, to the third gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a negative voltage relative to the voltage of the well to the control gate.
31. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate, to said third gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the well.
32. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of a p type; programming is made by applying a positive voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate, to the third gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to a voltage of the control gate to the source or the drain.
33. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a negative voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate, to the third gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the third gate.
34. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a negative voltage relative to voltages of the well and a source as one of the regions of the semiconductor region to a control gate as the second gate, to the third gate and to a drain as the other region of the semiconductor region; and erasing is made by applying a negative voltage relative to the voltage of the well to the control gate.
35. In an operation method of a semiconductor integrated circuit device including a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulation film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the well of the first conductivity type is of an n type; programming is made by applying a negative voltage relative to the well and a source as one of the regions of the semiconductor region to a control gate as the second gate and a drain as the other region of the semiconductor region; and erasing is made by applying a positive voltage relative to the voltage of the control gate to the well.
36. In an operation method of a semiconductor integrated circuit device according to any one of items 22 to 35, an absolute value of the third gate is smaller than that of the voltage of the control gate during the programming operation.
37. In an operation method of a semiconductor integrated circuit device according to any one of items 22 to 36, a distribution of the threshold value generated by the programming operation is at least four levels.
38. A method of producing a semiconductor integrated circuit device comprises the steps of: (a) forming a well of a first conductivity type in a semiconductor substrate; (b) forming a stripe-like pattern to serve as a first gate over the semiconductor substrate through a first insulator film; (c) forming a semiconductor region of a second conductivity type inside the well in such a manner as to extend in parallel with said pattern; (d) forming a third insulator film in the space defined by the stripe-like pattern, and burying a third gate into the space of the pattern; and (e) forming a second gate pattern in such a manner as to extend in a direction vertical to the stripe-like pattern.
39. In a method of producing a semiconductor integrated circuit device according to item 38, the strip-like pattern to function as the first gate is patterned in such a manner as to be symmetric with respect to the third gate, and the third gate is patterned in such a manner as to be symmetric with respect to the stripe-like pattern.
40. In a method of producing a semiconductor integrated circuit device according to item 39, the third gate is formed in self-alignment with the stripe-like pattern.
41. A method of producing a semiconductor integrated circuit device comprises the steps of: (a) forming a well of a first conductivity type inside a semiconductor substrate; (b) forming a first gate over the semiconductor substrate through a first insulator film; (c) forming a semiconductor region of a second conductivity type inside the well; (d) forming a third insulator film in a space defined by the first gate, and forming the third gate in such a manner as to bury the space of the pattern; and (e) forming a second gate, wherein said third gate is patterned so that the surface of the third gate is lower than the surface of the first gate.
42. A method of producing a semiconductor integrated circuit device according to any one of items 38 to 41, comprises any of the following methods: a first method of forming the third gate so that the entire surface of the third gate exists over the semiconductor region of the second conductivity type; and a second method of forming the third gate so that a part of the third gate exists over the semiconductor region of the second conductivity type.
43. In a method of producing a semiconductor integrated circuit device according to any one of items 38 to 41, the third gate is formed in such a manner that a part of the third gate exists over the semiconductor region of the second conductivity type, and the semiconductor region of the second conductivity type is formed by tilted ion implantation.
44. In a method of producing a semiconductor integrated circuit device according to any one of items 38 to 43, the third insulator film is a silicon oxide film doped with nitrogen.
45. In a method of producing a semiconductor integrated circuit device including a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, and a third gate formed and isolated from the first gate through a third insulator film: the second gate comprises a laminate film of a polysilicon film and a metal silicide film, and the formation of the second gate is conducted after the formation of the third gate.
46. In a method of producing a semiconductor integrated circuit device according to item 45, the metal silicide film is a tungsten silicide film.
47. In a method of producing a semiconductor integrated circuit device including a well of a first conductivity type formed on a main surface of a semiconductor substrate, a semiconductor region of a second conductivity type formed inside said well, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film and a third gate formed and isolated from the first gate through a third insulator film: the second gate comprises a laminate film containing a metal film.
48. In a method of producing a semiconductor integrated circuit device according to item 47, the second gate comprises a laminate film of a polysilicon film, a barrier metal film and a metal film.
49. In a method of producing a semiconductor integrated circuit device according to item 47 or 48, the third gate exists as it is buried into the space between said first gates.
50. In a method of producing a semiconductor integrated circuit device according to item 47, the barrier metal film belongs to a group of a tungsten film, a titanium film, a tantalum film, a metal film made of a transition metal itself or its nitride film or its silicide film, an aluminum nitride film, a cobalt silicide film, a molybdenum silicide film, a titanium tungsten film or their alloy films.
51. A semiconductor integrated circuit device includes a well of a first conductivity type formed in a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, local source lines and local data lines formed by connecting the semiconductor region, select transistors for selecting the local source lines and the local data lines, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed and isolated from the first gate through a second insulator film, word lines formed by connecting the second gates, and memory cells existing on the local source lines and the local data lines divided by the select transistors forming a memory cell block, the memory cell blocks being arranged in the direction of the word lines and constituting a memory cell array, wherein: one each power source line is disposed on both sides of the memory cell block to interpose the memory cell block in the same direction as the word lines; and the local source line and said local data line are connected to one of the power source lines and to a signal line arranged in a direction vertical to the word line, or to both of the power source lines, through the select transistor.
52. A semiconductor integrated circuit device according to item 51 has any one of the following constructions: a first construction wherein one of the local data lines is connected to both of the power source line and the signal line through the select transistor; and a second construction wherein one of the local data lines is connected to the signal line at one of the ends of the memory cell block through the select transistor, and an adjacent local data line adjacent to the one local data line is connected to the signal line at the other end of the memory cell block through the select transistor.
53. In a semiconductor integrated circuit device according to item 52 one of said local data lines is connected to the signal line at one of the ends of the memory cell block through the select transistor and to the power source line at the other end of the memory cell block through the select transistor.
54. In a semiconductor integrated circuit device according to item 53 which includes a first select transistor for connecting a signal line disposed in a direction vertical to the extending direction of the word line to an nth (n: integer) local data line, a second select transistor for connecting the power source line disposed at one of the ends of the memory cell block in the same direction as the word line to (n+1)th local data line, a third select transistor for connecting the signal line to the (n+1)th local data line, and a fourth select transistor for connecting the power source line disposed at the other end of the memory cell block in the same direction as the word line to the nth local data line: the gate signals of the first and second transistors are the same signals; and the gate signal of the third and fourth select transistors are the same signal.
55. A semiconductor integrated circuit device according to item 51 has any of the following constructions: a first construction wherein a gate signal of the select transistor connected to the local source line and a gate signal of the select transistor connected to the local data line are the same signal; and a second construction wherein gate signals of all of the select transistors connected to the local source lines are the same signal.
56. A semiconductor integrated circuit device includes a well of a first conductivity type formed in a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, local source/data lines formed by connecting the semiconductor region, select transistors for selecting the local source/data lines, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed and isolated from the first gate through a second insulator film, and word lines formed by connecting the second gate, wherein memory cells on the local source/data lines divided by the select transistors constitute memory cell blocks, and the memory cell blocks are arranged in the word line direction and constitute a memory cell array, and when the local source/data lines function as the local source lines of the memory cell, they function as the local data line of the memory cells adjacent to the memory cell, the semiconductor integrated circuit device including further one each power source line so disposed on both sides of the memory cell block as to interpose the memory cell block between them in the same direction as the word line, and signal lines disposed in a direction vertical to the word lines, the local source/data lines being connected to either one of said power source lines and to both of the signal lines through the select transistor.
57. A semiconductor integrated circuit device according to item 57 has any one of the following constructions: a first construction wherein nth (n: integer) local source/data line is connected to the signal line at one of the ends of the memory cell block through the select transistor and (n+1)th local source/data line is connected to the signal line at the other end of the memory cell block through the select transistor; and a second construction wherein an nth (n: integer) local source/data line is connected to the power source line at one of the ends of the memory cell block through the select transistor, and an (n+1)th local source/data line is connected to the power source line at the other end of the memory cell block through the select transistor.
58. In a semiconductor integrated circuit device according to item 56 or 57, one of the local source/data lines is connected to the signal line at one of the ends of the memory cell block through the select transistor, and to the power source line at the other end of the memory cell block through the select transistor.
59. A semiconductor integrated circuit device according to item 58 further includes a first select transistor for connecting the signal line wired in a direction vertical to the word line and an nth (n: integer) local source/data line, a second select transistor for connecting the power source line wired at one of the ends of the memory cell block in the same direction as the word line and an (n+1)th local source/data line, a third select transistor for connecting the signal line and the (n+1)th local source/data line and a fourth select transistor for connecting the power source line wired at the other end of the memory cell block in the same direction as the word line and said nth local source/data line, wherein: the gate signals of the first and second select transistors are the same signal, and the gate signals of the third and fourth select transistors are the same signal.
60. A semiconductor integrated circuit device according to any one of items 56 to 59 has any one of the following constructions: a first construction wherein one of the signal lines wired in a direction vertical to the word line is shared by two of the local source/data lines; a second construction wherein, when the local source/data line is connected to the signal line through the select transistor, the connection portion between the semiconductor region of the select transistor on the side different from the local source/data line and the signal line is shared by two of the memory cell blocks; and a third construction wherein the power source line is shared by two of the memory cell blocks.
61. A semiconductor integrated circuit device includes a well of a first conductivity type formed in a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, local source/data lines formed by connecting the semiconductor regions, select transistors for selecting the local source/data lines, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed and isolated from the first gate through a second insulator film, word lines formed by connecting the second gates, and a third gate formed and isolated from the first gate through a third insulator film and having a different function from those of the first and second gates, memory cells on the local source lines and local data lines divided by the select transistors constituting memory cell blocks, the memory cell blocks being arranged in the word line direction and constituting a memory cell array, wherein: a bundling portion of the third gates exists between the word line existing at the nearest position to the select transistor inside the memory cell block and the gate of the select transistor; every other third gates existing inside the memory cell block are bundled at one of the ends of the memory cell block; one each power source line are so disposed in the same direction as the word lines on both sides of the memory cell block as to interpose the memory cell block between them, and signal lines disposed in a direction vertical to the word lines; and the local source/data lines are connected to either one, or both, of the signal lines inside the power source line through the select transistor.
62. A semiconductor integrated circuit device according to item 61 has any one of the following constructions: a first construction wherein an nth (n: integer) local source/data line is connected to the signal line at one of the ends of the memory cell block through the select transistor, and an (n+1)th local source/data line is connected to the signal line at the other end of the memory cell block through the select transistor; and a second construction wherein an nth (n: integer) local source line is connected to the power source line at one of the ends of the memory cell block through the select transistor, and an (n+1)th local source/data line is connected to the power source line at the other end of the memory cell block through the select transistor.
63. In a semiconductor integrated circuit device according to item 61 or 62, one of the local source/data lines is connected to the signal line at one of the ends of the memory cell block through the select transistor, and is connected to the power source line at the other end of the memory cell block through the select transistor.
64. A semiconductor integrated circuit device according to item 63 further includes a first select transistor for connecting a signal line wired in a direction vertical to the word line and an nth (n: integer) local source/drain line, a second select transistor for connecting the power source line wired in the same direction as the word line to one of the ends of the memory cell block and an (n+1)th local source/data line, a third select transistor for connecting the signal line and the (n+1)th local source/date line and a fourth select transistor for connecting the power source line wired in the same direction as the word line and the nth local source/data line to the other end of the memory cell block, wherein: the gate signals of the first and second select transistors are the same signal; and the gate signals of the third and fourth select transistors are the same signal.
65. A semiconductor integrated circuit device according to any one of items 61 to 64 has any one of the following constructions: a first construction wherein one of the signal lines disposed in a direction vertical to the word line is shared by two of the local source/data lines; a second construction wherein, when the local source/data line and the signal line are connected through the select transistor, the connection portion between the semiconductor region of the select transistor on the side different from the local source/data line and the signal line is shared by two of the memory cell blocks; a third construction wherein the power source line is shared by two of the memory cell blocks; a fourth construction wherein the local source/data line is connected to the signal line wired in a direction vertical to the word line through the select transistor, a sense circuit is connected to the signal line, the sense circuit connected to an nth (n: integer) signal line is connected at one of the ends of a memory cell array comprising a plurality of memory cell blocks, and the sense circuit connected to an (n+1)th signal line is connected at the other end of the memory cell array; and a fifth construction wherein a switch is interposed between the signal line connected to the local source/data line through the select transistor and the sense circuit, and one sense circuit can be shared by a plurality of the signal lines when the switch is changed over.
66. A semiconductor integrated circuit device includes a well of a first conductivity type formed in a semiconductor substrate, a semiconductor region of a second conductivity type formed inside the well, local source/data lines formed by connecting the semiconductor region, select transistors for selecting the local source/data lines, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed and isolated from the gate through a second insulator film, word lines formed by connecting the second gates, and a third gate formed and isolated from the first gate through a third insulator film and having a different function from those of the first and second gates, memory cells on the local source lines and the local data lines divided by the select transistors constituting a memory cell block, the memory cell blocks being arranged in the word line direction and constituting a memory cell array, wherein: a bundling portion of the third gates exists between the word line existing at the nearest position to the select transistor inside the memory cell block and the select transistor; every other third gates existing inside the memory cell block are bundled at the end of the memory cell block; one each of the power source line arranged in the same direction as the word line and one each of the signal lines wired in a direction vertical to the word lines are so disposed on both sides of the memory cell block as to interpose the memory cell block between them; and the local source/data line is connected to both of the power source line and the signal line through the select transistor.
67. A semiconductor integrated circuit device according to item 66 has any one of the following constructions: a first construction wherein the local source/data line is connected to the signal line through the select transistor, and the connection is all made at one of the ends of the memory cell block; and a second construction wherein the local source/data line is connected to the power source line wired in the same direction as the word line at one of the ends of the cell block through the select transistor, and the connection is all made at one of the ends of the memory cell block.
68. In a semiconductor integrated circuit device according to item 66 or 67 one of the local source/data line is connected to the signal line at one of the ends of the memory cell block through the select transistor, and is connected to the power source line at the other end of the memory cell block through the select transistor.
69. In a semiconductor integrated circuit device according to item 68 which further includes a first select transistor for connecting the signal line wired in a direction vertical to the word line and an nth (n: integer) local source/data line, a second select transistor for connecting the signal line and an (n+1)th local source/data line, a third select transistor for connecting the power source line wired in the same direction as the word line and the nth local source/data line at the other end of the memory cell block, and a fourth select transistor for connecting the power source line and the (n+1)th local source/data line; the gate signals of all of the first select transistors are the same signal; the gate signals of all of the second select transistors are the same signal; the gate signals of the first and second select transistors are different signals, and the gate signals of all of the third select transistors are the same signal; the gate signals of all of the fourth select transistors are the same signal; and the gate signals of the third and fourth gate signals are different signals.
70. A semiconductor integrated circuit device according to any one of items 66 to 69 has any one of the following constructions: a first construction wherein two of the local source/data lines share the signal line; a second construction wherein, when the local source/data line and said signal line are connected through the select transistor, the connection portion of the semiconductor region of the select transistor on the side different from the local source/data line and the signal line is shared by two of the memory cell blocks; a third construction wherein two of the memory cell blocks share the power source line; a fourth construction wherein the local source/data line is connected to the signal line through the select transistor, the sense circuit is connected to the signal line, the sense circuit to be connected to nth (n: integer) signal line is connected at one of the ends of the memory cell array comprising a plurality of memory cell blocks, the sense circuit to be connected to (n+1)th signal line is connected at the other end of the memory cell array; and a fifth construction wherein a switch is interposed between the signal line connected to the local source/data line through the select transistor and the sense circuit, and one sense circuit is shared by a plurality of the signal lines as the switch is changed over.
71. A semiconductor integrated circuit device includes a well of a first conductivity type formed in a main surface of a semiconductor substrate, a semiconductor region of a second contuctivity type formed inside the well in such a manner as to extend in a first direction, a first gate formed over the semiconductor substrate through a first insulator film, a second gate formed over the first gate through a second insulator film, word lines formed by connecting the second gate, and a third gate formed and isolated from the first gate through a third insulator film, the third gate being buried in a space of the first gate existing in a direction vertical to the word line, wherein: a decoder for driving the third gate is disposed in the extending direction of the word line.
72. A semiconductor integrated circuit device according to item 71 has any one of the following constructions: a first construction wherein the decoder for driving the third gate is disposed at one of the ends of a memory cell array; a second construction wherein the decoder for driving the third gate is disposed adjacent to a block decoder for selecting memory cell blocks each comprising memory cell arrays existing on a plurality of word lines encompassed by the select transistors; and a third construction wherein the decoders for driving the third gates are disposed on both sides of the memory cell while interposing the memory cell array between them and adjacent to a block decoder for selecting the memory cell blocks.
73. In a semiconductor integrated circuit device according to item 20 the third gate is formed as it is buried into the space between the first gates extending in a direction vertical to the word line; and a decoder for driving the third gate is disposed in an extending direction of the word line.
74. A semiconductor integrated circuit device according to item 73 has any one of the following constructions: a first construction wherein the decoder for driving the third gate is disposed at one of the ends of the memory cell array; a second construction wherein the decoder for driving the third gate is disposed adjacent to a block decoder for selecting the memory cell block; and a third construction wherein the decoders for driving the third gate are so disposed on both sides of the memory cell arrays as to interpose the memory cell array between them, adjacent to the block decoder for selecting the memory cell block.
75. In a semiconductor integrated circuit device according to item 18 or 19 wherein all of the third gates existing inside the memory cell block are bundled at either one, or both, of the ends of the memory cell block, the selection signal of the third gate is generated from a selection signal of the memory cell block.
76. A semiconductor integrated circuit device according to item 18 or 19, wherein all of the third gates existing inside the memory cell block are bundled at either one, or both, of the ends of the memory cell block, has any one of the following construction: a first construction wherein the selection signal of the third gate is generated from a selection signal of the memory cell block and a signal for further halving the memory cell block; and a second construction wherein the selection signal of the third gate is generated from a gate selection signal of the select transistor.